Embodiments of the present invention relate to methods for fabricating chalcogenide memory. More particularly, embodiments of the present invention relate to methods for decreasing the contact area and forming the isolation of a chalcogenide memory cell.
Multimedia applications for communication devices, computers, and consumer electronics are increasing the demand for memory devices. These applications are also increasing the requirements the memory devices must meet. Increased memory device requirements include but are not limited to high density, non-volatility, fast access speeds, low power consumption, and good endurance. Memory device technologies currently being developed to satisfy these requirements include but are not limited to flash, magnetic or magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), and chalcogenide memory. Chalcogenide memory can include but is not limited to Ovonic Unified Memory™ (OUM™), from ECD Ovonics of Rochester Hill, Mich., for example. Chalcogenide memory is a particularly promising technology due to its low cost, manufacturability, electrically writeable and directly erasable low input energies, multi-bit capability, non-volatility, and very high packing density.
Chalcogenide materials are materials that can be electrically switched from a generally amorphous state, to a generally crystalline state, and back to a generally amorphous state. Chalcogenide materials exhibit different electrical characteristics depending on their state. For example, a chalcogenide material exhibits lower electrical conductivity in its amorphous state than it does in its crystalline state. The switching and electrical characteristics of chalcogenide devices make chalcogenide materials useful in fabricating memory devices.
A memory device made from a chalcogenide material generally includes a lower electrode, a thin film of chalcogenide material, an upper electrode, and a dielectrics material for isolation from other memory devices. The chalcogenide material is the memory element of the memory device. The operation and use of chalcogenide materials as memory devices has been described, for example, in U.S. Pat. No. 5,296,716 to Ovshinsky et al., the disclosure of which is incorporated herein by reference.
One advantage of using chalcogenide materials is their low current and energy requirements for electrical switching. In a chalcogenide memory cell, the portion of the chalcogenide material that is switched to either the high or low resistance state is called the “filamentary portion.” Generally, the “filamentary portion” corresponds to the cross-sectional area of the memory cell. Thus the “filamentary portion” is limited by lithography. In some chalcogenide memory devices, however, the “filamentary portion” can be reduced to an area that is less than the cross-sectional area of the memory cell. This can further reduce the current and energy requirements for switching.
One method of reducing the “filamentary portion” of a chalcogenide memory cell is to form smaller volumes, called “plugs,” of lower resistivity in the two contacts on either side of the chalcogenide layer as disclosed, for example, in U.S. Pat. No. 6,545,903 to Wu, the disclosure of which is incorporated herein by reference. Another method of reducing “filamentary portion” is to deposit a chalcogenide material on the vertical sidewalls of two horizontal contacts separated by an insulator as disclosed, for example, in U.S. Pat. No. 6,830,952 to Lung, the disclosure of which is incorporated herein by reference. And another method of reducing the “filamentary portion” of a chalcogenide memory cell is to fabricate one of the contacts in the form of a tapered contact such that the peak of the tapered contact is adjacent to the chalcogenide layer as disclosed, for example, in U.S. Pat. No. 5,687,112 to Ovshinsky, the disclosure of which is incorporated herein by reference.
In view of the foregoing, it can be appreciated that a substantial need exists for systems and methods that can advantageously increase the packing density and performance of chalcogenide memory devices.